FS's Plot 2

The Field Programmable Gate Array, or FPGA is a type of device that is widely used in the logic or digital electronic circuits. FPGAs are semiconductor devices that contain programmable logic and interconnections. The programmable logic components, or logic blocks as they are known, may consist of anything from logic gates, through to memory elements or blocks of memories, or almost any element.

There are many forms of devices which are field programmable. These are PAL, PLD, CPLD, and FPGA. These devices differ on their granularity, how the programming is accomplished etc. PAL, PLA and CPLD devices are usually smaller in capacity but more predictable in timing and they can be implemented with Sum-of-Products, Product-of-Sums or both. FPGA devices can be based on Flash, SRAM, EEPROM or Anti-Fuse connectivity. The most successful FPGA devices are based on SRAM. This is because all other memory types are much less dense in terms of area than SRAM. Also some types of connectivity are One-Time Programmable (i.e. Anti-Fuse) so they are not very flexible. SRAM based FPGAs have no maximum erase cycle limitations either.

The great advantage of the FPGA is that the chip is completely programmable and can be re-programmed. In this way it becomes a large logic circuit that can be configured according to a design, but if changes are required it can be re-programmed with an update. Thus if circuit card or board is manufactured and contains an FPGA as part of the circuit, this is programmed during the manufacturing process, but can later be re-programmed to reflect any changes. Thus it is field programmable, giving rise to its name.

Although FPGAs offer many advantages, there are naturally some disadvantages. They are slower than equivalent ASICs (Application Specific Integrated Circuit) or other equivalent ICs, and additionally they are more expensive. (However ASICs are very expensive to develop by comparison). This means that the choice of whether to use an FPGA based design should be made early in the design cycle and will depend on such items as whether the chip will need to be re-programmed, whether equivalent functionality can be obtained elsewhere, and of course the allowable cost. Sometimes manufacturers may opt for an FPGA design for early product when bugs may still be found, and then use an ASIC when the design is fully stable.

FPGAs are used in many applications. In view of the cost they are not used in cheap high volume products, but instead FPGAs find applications in a variety of areas where complex logic circuitry may be needed, and changes may be anticipated. FPGA applications cover a wide range of areas from equipment for video and imaging, to circuitry for aerospace and military applications, as well as electronics for specialized processing and much more.

FPGA internals

The internal architecture of the FPGA is the key to its flexibility and hence its success. Essentially an FPGA consists of two basic elements:

* An array of Common Logic Blocks (CLB)

* Routing channels

Logic block in an FPGA: The logic block in an FPGA can be implemented in variety of ways. The actual implementation depends upon the manufacturer and also the series of FPGA being used. The variations include the number of inputs and outputs, the general complexity of the logic block in terms of circuitry and the number of transistors used. This naturally has an impact on the amount of area consumed on the chip, and hence the size the silicon used.

FPGA internal routing: The routing within the FPGA comprises wires that cane be interconnected using electrically configurable switches. In this way it is possible to link different points on the chip together and thereby connect the different Common Logic Blocks in whatever way is required.

Designing with FPGAs

In view of the complexity of FPGAs, software is used to design the function of an FPGA. The FPGA design process is started by the user providing a Hardware Description Language (HDL) definition or a schematic design.

Common HDLs are VHDL (where VHDL stands for VHSIC Hardware Description Language) and Verilog. Once this has been completed the next task in the FPGA design process is to produce a netlist is generated for the particular FPGA family being used. This describes the connectivity required within the FPGA and it is generated using an electronics design automation tool.

The netlist can then be fitted to the actual FPGA architecture using a process called place-and-route, usually performed by the FPGA company's proprietary place-and-route software.

Finally the design is committed to the FPGA and it can be used in the electronic circuit board for which it is intended.

FPGA testing

In view of their complexity, it is necessary to undertake rigorous testing of the FPGA design. This testing will normally be undertaken at each stage of the FPGA development process. It includes timing analysis, functional simulation, and other verification methodologies. Once the design and validation process is complete, the binary file generated (also using the FPGA company's proprietary software) is used to configure the FPGA device.
FPGA tools

The tools for developing and testing FPGAs are available from a variety of sources. Obviously the manufacturer is able to offer many FPGA development tools, but there are many other sources for third party FPGA HDL synthesis, FPGA physical synthesis and verification tools. These include the actual development and for the various stages of testing of the FPGAs.

FPGA development is in some sense similar to ASIC development. One can talk about Front-End Tools which can be Schematic Entry or an HDL (Hardware Description Language). Most common HDLs used for FPGA Design are Verilog and VHDL. After describing an FPGA design in an HDL, a tool called a Synthesizer which effectively converts Verilog, VHDL into the specific primitives which exist an an FPGA family. SRAM based FPGAs have Lookup-Tables which can be programmed to implement any function of N variables (usually 4~5) and Flip-Flops which can be programmed to implement different types of storage (JK, T, Latch, DFF with set and/or reset etc).

After a device level netlist is generated with synthesis, one uses a back-end tool called Place & Route which is most of the time supplied by the device vendor (i.e. Xilinx or Altera). In contrast synthesis tools are usually supplied by third party vendors and even the ones packaged with vendors' toolset usually are restricted versions of third party tools. Most popular synthesis tools come from Synplicity, Exemplar, Cadence and Synopsys. DSPIA Inc. suggests Synplicity for FPGA development because of their high quality tools.

Most synthesis tools understand only a subset of HDLs which are synthesizable subsets. Up until recently these subsets weren't standardized and varied from vendor to vendor. These days there are efforts under way to standardize synthesizable Verilog and VHDL code. A good site for Verilog or VHDL is EDA.ORG

From the P&R tool, one obtains a file which can be used to download onto an FPGA to program it with the hardware design described by the original HDL code. This download can be either done through a serial connection, a JTAG cable or programmed into a ROM and loaded into the FPGA every time power is applied. This is very roughly the flow of FPGA development. We'll go into more detail of every step and give simple examples using an Xilinx FPGA, Verilog and Synplify Synthesizer from Synplicity.